mirror of
https://github.com/shenmintao/aic8800d80.git
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300 lines
8.1 KiB
C
300 lines
8.1 KiB
C
/**
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****************************************************************************************
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*
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* @file rwnx_ipc_app.h
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*
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* @brief IPC module register definitions
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*
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* Copyright (C) RivieraWaves 2011-2019
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*
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****************************************************************************************
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*/
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#ifndef _REG_IPC_APP_H_
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#define _REG_IPC_APP_H_
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#ifndef __KERNEL__
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#include <stdint.h>
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#include "arch.h"
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#else
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#include "ipc_compat.h"
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#endif
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#include "reg_access.h"
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#define REG_IPC_APP_DECODING_MASK 0x0000007F
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/**
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* @brief APP2EMB_TRIGGER register definition
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* <pre>
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* Bits Field Name Reset Value
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* ----- ------------------ -----------
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* 31:00 APP2EMB_TRIGGER 0x0
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* </pre>
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*/
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#define IPC_APP2EMB_TRIGGER_ADDR 0x12000000
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#define IPC_APP2EMB_TRIGGER_OFFSET 0x00000000
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#define IPC_APP2EMB_TRIGGER_INDEX 0x00000000
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#define IPC_APP2EMB_TRIGGER_RESET 0x00000000
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__INLINE u32 ipc_app2emb_trigger_get(void *env)
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{
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return REG_IPC_APP_RD(env, IPC_APP2EMB_TRIGGER_INDEX);
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}
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__INLINE void ipc_app2emb_trigger_set(void *env, u32 value)
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{
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REG_IPC_APP_WR(env, IPC_APP2EMB_TRIGGER_INDEX, value);
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}
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// field definitions
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#define IPC_APP2EMB_TRIGGER_MASK ((u32)0xFFFFFFFF)
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#define IPC_APP2EMB_TRIGGER_LSB 0
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#define IPC_APP2EMB_TRIGGER_WIDTH ((u32)0x00000020)
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#define IPC_APP2EMB_TRIGGER_RST 0x0
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__INLINE u32 ipc_app2emb_trigger_getf(void *env)
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{
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u32 localVal = REG_IPC_APP_RD(env, IPC_APP2EMB_TRIGGER_INDEX);
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ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
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return (localVal >> 0);
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}
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__INLINE void ipc_app2emb_trigger_setf(void *env, u32 app2embtrigger)
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{
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ASSERT_ERR((((u32)app2embtrigger << 0) & ~((u32)0xFFFFFFFF)) == 0);
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REG_IPC_APP_WR(env, IPC_APP2EMB_TRIGGER_INDEX, (u32)app2embtrigger << 0);
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}
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/**
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* @brief EMB2APP_RAWSTATUS register definition
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* <pre>
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* Bits Field Name Reset Value
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* ----- ------------------ -----------
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* 31:00 EMB2APP_RAWSTATUS 0x0
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* </pre>
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*/
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#define IPC_EMB2APP_RAWSTATUS_ADDR 0x12000004
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#define IPC_EMB2APP_RAWSTATUS_OFFSET 0x00000004
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#define IPC_EMB2APP_RAWSTATUS_INDEX 0x00000001
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#define IPC_EMB2APP_RAWSTATUS_RESET 0x00000000
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__INLINE u32 ipc_emb2app_rawstatus_get(void *env)
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{
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return REG_IPC_APP_RD(env, IPC_EMB2APP_RAWSTATUS_INDEX);
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}
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__INLINE void ipc_emb2app_rawstatus_set(void *env, u32 value)
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{
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REG_IPC_APP_WR(env, IPC_EMB2APP_RAWSTATUS_INDEX, value);
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}
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// field definitions
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#define IPC_EMB2APP_RAWSTATUS_MASK ((u32)0xFFFFFFFF)
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#define IPC_EMB2APP_RAWSTATUS_LSB 0
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#define IPC_EMB2APP_RAWSTATUS_WIDTH ((u32)0x00000020)
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#define IPC_EMB2APP_RAWSTATUS_RST 0x0
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__INLINE u32 ipc_emb2app_rawstatus_getf(void *env)
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{
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u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_RAWSTATUS_INDEX);
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ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
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return (localVal >> 0);
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}
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/**
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* @brief EMB2APP_ACK register definition
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* <pre>
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* Bits Field Name Reset Value
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* ----- ------------------ -----------
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* 31:00 EMB2APP_ACK 0x0
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* </pre>
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*/
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#define IPC_EMB2APP_ACK_ADDR 0x12000008
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#define IPC_EMB2APP_ACK_OFFSET 0x00000008
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#define IPC_EMB2APP_ACK_INDEX 0x00000002
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#define IPC_EMB2APP_ACK_RESET 0x00000000
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__INLINE u32 ipc_emb2app_ack_get(void *env)
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{
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return REG_IPC_APP_RD(env, IPC_EMB2APP_ACK_INDEX);
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}
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__INLINE void ipc_emb2app_ack_clear(void *env, u32 value)
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{
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REG_IPC_APP_WR(env, IPC_EMB2APP_ACK_INDEX, value);
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}
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// field definitions
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#define IPC_EMB2APP_ACK_MASK ((u32)0xFFFFFFFF)
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#define IPC_EMB2APP_ACK_LSB 0
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#define IPC_EMB2APP_ACK_WIDTH ((u32)0x00000020)
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#define IPC_EMB2APP_ACK_RST 0x0
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__INLINE u32 ipc_emb2app_ack_getf(void *env)
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{
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u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_ACK_INDEX);
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ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
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return (localVal >> 0);
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}
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__INLINE void ipc_emb2app_ack_clearf(void *env, u32 emb2appack)
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{
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ASSERT_ERR((((u32)emb2appack << 0) & ~((u32)0xFFFFFFFF)) == 0);
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REG_IPC_APP_WR(env, IPC_EMB2APP_ACK_INDEX, (u32)emb2appack << 0);
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}
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/**
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* @brief EMB2APP_UNMASK_SET register definition
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* <pre>
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* Bits Field Name Reset Value
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* ----- ------------------ -----------
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* 31:00 EMB2APP_UNMASK 0x0
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* </pre>
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*/
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#define IPC_EMB2APP_UNMASK_SET_ADDR 0x1200000C
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#define IPC_EMB2APP_UNMASK_SET_OFFSET 0x0000000C
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#define IPC_EMB2APP_UNMASK_SET_INDEX 0x00000003
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#define IPC_EMB2APP_UNMASK_SET_RESET 0x00000000
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__INLINE u32 ipc_emb2app_unmask_get(void *env)
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{
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return REG_IPC_APP_RD(env, IPC_EMB2APP_UNMASK_SET_INDEX);
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}
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__INLINE void ipc_emb2app_unmask_set(void *env, u32 value)
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{
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REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_SET_INDEX, value);
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}
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// field definitions
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#define IPC_EMB2APP_UNMASK_MASK ((u32)0xFFFFFFFF)
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#define IPC_EMB2APP_UNMASK_LSB 0
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#define IPC_EMB2APP_UNMASK_WIDTH ((u32)0x00000020)
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#define IPC_EMB2APP_UNMASK_RST 0x0
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__INLINE u32 ipc_emb2app_unmask_getf(void *env)
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{
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u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_UNMASK_SET_INDEX);
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ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
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return (localVal >> 0);
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}
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__INLINE void ipc_emb2app_unmask_setf(void *env, u32 emb2appunmask)
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{
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ASSERT_ERR((((u32)emb2appunmask << 0) & ~((u32)0xFFFFFFFF)) == 0);
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REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_SET_INDEX, (u32)emb2appunmask << 0);
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}
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/**
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* @brief EMB2APP_UNMASK_CLEAR register definition
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* <pre>
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* Bits Field Name Reset Value
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* ----- ------------------ -----------
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* 31:00 EMB2APP_UNMASK 0x0
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* </pre>
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*/
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#define IPC_EMB2APP_UNMASK_CLEAR_ADDR 0x12000010
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#define IPC_EMB2APP_UNMASK_CLEAR_OFFSET 0x00000010
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#define IPC_EMB2APP_UNMASK_CLEAR_INDEX 0x00000004
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#define IPC_EMB2APP_UNMASK_CLEAR_RESET 0x00000000
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__INLINE void ipc_emb2app_unmask_clear(void *env, u32 value)
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{
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REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_CLEAR_INDEX, value);
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}
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// fields defined in symmetrical set/clear register
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__INLINE void ipc_emb2app_unmask_clearf(void *env, u32 emb2appunmask)
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{
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ASSERT_ERR((((u32)emb2appunmask << 0) & ~((u32)0xFFFFFFFF)) == 0);
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REG_IPC_APP_WR(env, IPC_EMB2APP_UNMASK_CLEAR_INDEX, (u32)emb2appunmask << 0);
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}
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/**
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* @brief EMB2APP_STATUS register definition
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* <pre>
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* Bits Field Name Reset Value
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* ----- ------------------ -----------
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* 31:00 EMB2APP_STATUS 0x0
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* </pre>
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*/
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#ifdef CONFIG_RWNX_OLD_IPC
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#define IPC_EMB2APP_STATUS_ADDR 0x12000014
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#define IPC_EMB2APP_STATUS_OFFSET 0x00000014
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#define IPC_EMB2APP_STATUS_INDEX 0x00000005
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#else
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#define IPC_EMB2APP_STATUS_ADDR 0x1200001C
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#define IPC_EMB2APP_STATUS_OFFSET 0x0000001C
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#define IPC_EMB2APP_STATUS_INDEX 0x00000007
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#endif
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#define IPC_EMB2APP_STATUS_RESET 0x00000000
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__INLINE u32 ipc_emb2app_status_get(void *env)
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{
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return REG_IPC_APP_RD(env, IPC_EMB2APP_STATUS_INDEX);
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}
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__INLINE void ipc_emb2app_status_set(void *env, u32 value)
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{
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REG_IPC_APP_WR(env, IPC_EMB2APP_STATUS_INDEX, value);
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}
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// field definitions
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#define IPC_EMB2APP_STATUS_MASK ((u32)0xFFFFFFFF)
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#define IPC_EMB2APP_STATUS_LSB 0
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#define IPC_EMB2APP_STATUS_WIDTH ((u32)0x00000020)
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#define IPC_EMB2APP_STATUS_RST 0x0
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__INLINE u32 ipc_emb2app_status_getf(void *env)
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{
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u32 localVal = REG_IPC_APP_RD(env, IPC_EMB2APP_STATUS_INDEX);
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ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
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return (localVal >> 0);
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}
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/**
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* @brief APP_SIGNATURE register definition
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* <pre>
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* Bits Field Name Reset Value
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* ----- ------------------ ----------
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* 31:00 APP_SIGNATURE 0x0
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* </pre>
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*/
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#define IPC_APP_SIGNATURE_ADDR 0x12000040
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#define IPC_APP_SIGNATURE_OFFSET 0x00000040
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#define IPC_APP_SIGNATURE_INDEX 0x00000010
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#define IPC_APP_SIGNATURE_RESET 0x00000000
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__INLINE u32 ipc_app_signature_get(void *env)
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{
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return REG_IPC_APP_RD(env, IPC_APP_SIGNATURE_INDEX);
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}
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__INLINE void ipc_app_signature_set(void *env, u32 value)
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{
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REG_IPC_APP_WR(env, IPC_APP_SIGNATURE_INDEX, value);
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}
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// field definitions
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#define IPC_APP_SIGNATURE_MASK ((u32)0xFFFFFFFF)
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#define IPC_APP_SIGNATURE_LSB 0
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#define IPC_APP_SIGNATURE_WIDTH ((u32)0x00000020)
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#define IPC_APP_SIGNATURE_RST 0x0
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__INLINE u32 ipc_app_signature_getf(void *env)
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{
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u32 localVal = REG_IPC_APP_RD(env, IPC_APP_SIGNATURE_INDEX);
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ASSERT_ERR((localVal & ~((u32)0xFFFFFFFF)) == 0);
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return (localVal >> 0);
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}
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#endif // _REG_IPC_APP_H_
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